In a host computing system a variety of interconnects may be used to interconnect components, one to another. Therefore, a variety of communications may occur between components via the interconnects. When a component device needs attention of the host or when an error occurs, for instance, interrupt messages may be communicated via the interconnects to signal to the host to attend to the device, such as by providing processing time or other resources. One traditional technique to process these interrupt messages is for the host, when the interrupt is due to be processed, to access data regarding the interrupts from memory of the component generating the interrupt. However, this access of interrupt data from a component via the interconnect may be relatively slow, which often results in delays and “ties up” the resources of the host.